The present invention relates generally to semiconductor fabrication and more specifically to methods of cleaning a semiconductor wafer before and after low-doped drain (LDD) implantation.
Complimentary metal-oxide semiconductor (CMOS) technology demands channel length scaling beyond 0.1 xcexcm and brings new challenges to channel/source/drain engineering by conventional implant technology.
Wet clean processes must be free from silicon (Si) recessing, that is wet clean processes should not also consume the silicon the processes are cleaning. This is particularly important for post implantation to reduce the implantation dose loss or the dose variation induced electrical instability.
U.S. Pat. No. 6,150,277 to Torek describes a method of using TMAH to etch an implanted area.
U.S. Pat. No. 6,214,682 B1 to Wang describes a process to reduce transient enhanced diffusion (TED) using an anneal.
U.S. Pat. No. 4,652,334 to Jain et al., U.S. Pat. No. 5,690,322 to Xiang et al., U.S. Pat. No. 5,486,266 to Tsai et al. and U.S. Pat. No. 5,811,334 to Buller et al. describe related methods.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of LDD implant cleaning.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate structure formed thereover is provided. The substrate is cleaned by a wet clean process including NH4OH. An LDD implantation is performed into the substrate to form LDD implants. The substrate is cleaned by a wet clean process excluding NH4OH.